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  My working Genetic Algorithm  (Read 13025 times)
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Offline K.I.L.E.R

Senior Devvie

Java games rock!

« Reply #30 - Posted 2005-09-05 08:45:14 »

Ahh. I mistook what a local optima was.
If that's the case then EP should be used elsewhere or differently.

Is there a name for a "redneck" programmer?

Unemployed. Wink
Offline blahblahblahh

JGO Coder

Medals: 1

« Reply #31 - Posted 2005-09-05 14:16:24 »

What makes you think that local optimum is anywhere near what a human is capable of? That local optimum might as well be running into a wall for most of the time.

If you're EP gets stuck in a local optimum, you are not a competent EP programmer. It's a problem that was solved around 20 years ago, so I really dont think it's something to be worrying about in the 21st century.

malloc will be first against the wall when the revolution comes...
Offline Raghar

Junior Devvie

Ue ni taete 'ru hitomi ni kono mi wa dou utsuru

« Reply #32 - Posted 2005-09-06 20:11:06 »

What? Travelling salesman problem has been solved optimally? I wasn't aware about that.

As for GA for JVM. That would do more harm than effectivity increase. CPU pipelines are fixed and optimalization isn't as difficult. If someone would do compiler for some better computer like Hero, they might have some reasons for it, but they should be careful to avoid Hero's internal recompiler that could be dazzled by "improvements" in code.

The way to improve compilers isn't only in development a better smarter compilers, but also in forcing the CPU developers to accept some rules, and add some needed functionality to new CPUs.
Fast random memory access is one of needed things. There are others, barrel shifter (reintroduced for Prescotts after it was for strange reasons removed in Northwoods), low cache latency, addressable cache, multicore CPUs, low energy consumption, forcing developers to use instructions for memory addressing to memory addressing (by, for example, address cache possibly out of register), implementing some reasonable timer independent on CPU cycles and as much as possible on temperature of system, cache for thread states, improving bandwidth between CPU and other components, improving memory controller, or doubling memory controller, to avoid multiCPU write storms, and also increasing of parellelization on XMM registers (2x1 SIMD instruction is pretty low end).

Current situation is Intel or AMD add something, then pretend its useful for something completely else than would be reasonable, and then everyone needs to bite and try invent a way how it could be reasonably used.

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